［徵才］Mentor Graphics 愛爾蘭商明導國際(股)公司台灣分公司
公司網站 http://www.mentorg.com.tw/company/
Position: Associate Applications Engineer - DVT
Location: HsinChu, Taiwan
Job Description:
Mentor Graphics is a global technology leader in Electronic Design Automation, providing software and hardware design solutions that help engineers around the world innovate. Each year, our customers use tools of Mentor Graphics to push the boundaries of technology to deliver smaller, faster and more reliable products. They trust us with their technologies, we trust you to make them better.
In this position, you will be involved in a structured Associate Application Engineer Training Program. This is a fast-track training program that challenges you to develop the expertise needed to solve difficult technical problems. Associate Application Engineers are members of a team of highly motivated individuals working with customers designing the most complex hardware and software systems in the world and whose applications span the electronics industry. This training program will give you unique insight into our sales organization. Upon successful completion of the training program, you will be eligible to advance into Field Application Engineer position.
Job Qualification
1 year (or less) experience (in school) related with register-transfer-level (RTL) digital logic design, functional verification methodology, FPGA, ESL, and emulation is a plus.
* Verilog HDL simulation, verification methodology and language such as System Verilog, UVM, OVM, & SVA as a must
* IP level verification experience is a must
* Full chip level verification experience is a plus
* UPF Power & Power aware simulation related experience as a plus
* Static verification experience such as CDC, and Formal as a plus
* Testbench Automation, and coverage-driven verification
* Simulation acceleration & emulation as a plus
* ESL architectural design & virtual platform as a plus
* Communicate effectively in verbal and written form in English
* Build strong rapport and credibility with customer organizations while maintaining a company internal network of contacts
* With strong communications and interpersonal skills
Desirable Qualifications:
* System Verilog, OVM, UVM, SVA
* SystemC, C/C++, Tcl/TK, PERL
* Synthesis, SDC and static timing analysis as a plus Bachelor degree in EE and related field required.
* Strong written and oral communications in the English language is a plus
Contact Window: Sophie Wu 伍芳萱 l Human Resources
DID: +886-3-513-1091 l sophie_wu@mentor.com l Mentor Graphics明導國際
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